The present disclosure relates to a semiconductor device and is used appropriately for, e.g., a semiconductor device including a level shifter.
A technique is known in which, to a cross-coupled level shifter, a clamp MOS transistor for exceeded-breakdown-voltage prevention is added to prevent a voltage of not less than the breakdown voltage from being applied to each of MOS (Metal Oxide Semiconductor) transistors.
For example, the level shifter disclosed in FIG. 1 of Japanese Unexamined Patent Application Publication No. Hei 9(1997)-172368 (Patent Document 1) includes a clamp circuit for exceeded-breakdown-voltage prevention which clamps an intermediate potential, a latch circuit which operates between a high-potential power supply and a clamp potential, and a latch inversion circuit which operates between the clamp potential and a ground potential.
Specifically, the latch circuit includes first and second PMOS (P-channel MOS) transistors having respective sources coupled to the high-potential power supply and respective drains and gates cross-coupled together.
The clamp circuit includes third and fourth PMOS transistors respectively coupled in series to the foregoing first and second PMOS transistors and first and second NMOS (N-channel MOS) transistors respectively coupled in series to the third and fourth PMOS transistors. To the gate of each of these transistors, the clamp potential is applied. The clamp circuit will be hereinafter referred to also as an exceeded-breakdown-voltage prevention circuit.
The latch inversion circuit includes third and fourth NMOS transistors respectively coupled between the first and second NMOS transistors and the ground potential. To the gates of the third and fourth NMOS transistors, complementary input signals are input. The latch inversion circuit will be hereinafter referred to also as an input circuit.